1. Field of the Invention
The present invention relates to a semiconductor system, and more particularly relates to a semiconductor system including a plurality of controlled chips and controlling chips that control the controlled chips.
2. Description of the Related Art
A memory capacity that is required in a semiconductor device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor device that has a large memory capacity and a high operation speed as a whole.
However, this kind of semiconductor device is recognized as only one memory chip, in view of a controller. For this reason, when the plural core chips are allocated to one interface chip, how to perform an individual access to each core chip becomes a problem. In the case of the general multi-chip package, each memory chip is individually selected using a dedicated chip selection terminal (/CS) in each memory chip. Meanwhile, in the semiconductor device described above, since the chip selection terminal is provided in only the interface chip, each core chip cannot be individually selected by a chip selection signal.
In order to resolve this problem, JP-A No. 2007-157266 described above, a chip identification number is allocated to each core chip, a chip selection address is commonly provided from the interface chip to each core chip, and individual selection of each core chip is realized.
In Japanese Patent Application Laid-open No. 2007-157266 discloses an arrangement in which core chips (DRAM chips) are stacked in five layers, an interface chip is stacked on the topmost layer of the core chips, and these chips are connected to each other via through silicon vias. To achieve such a chip-stacked semiconductor device, chips are individually manufactured, and are stacked and packaged after they are tested for defects.
Sometimes defective core chips are found during checking after assembling the chips. In this case, discarding the entire chip-stacked semiconductor device is not always necessary because the remaining core chips and the interface chip are operating normally. There is a need of a method for relieving normally functioning core chips by obtaining a so-called partial product in which the semiconductor device itself is not considered as defective even though a portion of the core chips is defective by operating only the normally functioning core chips without using the defective core chips. Although not related to the chip-stacked semiconductor device, techniques of using the so-called partial product are disclosed in Japanese Patent Application Laid-open Nos. H9-128995 and H9-161497.
However, in the methods disclosed in Japanese Patent Application Laid-open Nos. H9-128995 and H9-161497, an output of an internal voltage generating circuit is also supplied to an unused area. Therefore, unnecessarily power is consumed by the internal voltage generating circuit itself, and there is also a problem that a leakage current is produced in the unused area. These problems are not limited to chip-stacked semiconductor devices, but also occur in a general semiconductor system including a plurality of controlled chips and controlling chips that control the controlled chips.